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We Compute Radically Different.


About SRC

SRC Labs is a recognized leader in the design and development of general-purpose dynamically reconfigurable computing and has been deploying powerful programmer-friendly servers, workstations and embedded systems for over a decade. Our systems deliver dramatic performance gains while using far less energy in a much smaller footprint that traditional inefficient CPU clusters.

History

The legendary computer architect Seymour R. Cray founded SRC in 1996 with a core team of senior engineers from Cray Research to continue his legacy of innovation. The Company name originates from the initials of Seymour's name. The Company's mission was to provide an affordable, high performance computer that targeted traditional supercomputing customers, primarily those who used scientific and engineering applications.

Mr. Cray's designs were noteworthy for their meticulous attention to the way the data moves inside the computer, and he focused on building systems that provided large shared memory, fast commodity processors and high bandwidth I/O. SRC systems also utilized off-the-shelf technology, which vastly reduced development time and cost while providing a unique approach towards designing and manufacturing high performance computer systems. This allowed SRC to move far beyond the term supercomputer, which implies an enormous price tag and large system footprint, and the Company's product line grew to include desktop, mobile and embedded systems.

Mr. Cray was ultimately succeeded by Jon Huppenthal, Mr. Cray's protégé, and SRC continued to pioneer the path for FPGA-based acceleration in search, cryptography, and image, network and data flow processing. Mr. Huppenthal keenly focused SRC's efforts on providing solutions that went beyond just the instruction processor — leveraging reconfigurable processors to unlock the optimization of logic only possible with FPGAs.

Technology

SRC Labs has developed a system architecture that tightly couples the computational potential of both microprocessors and reconfigurable processors. SRC's Carte™ Programming Environment fully integrates the compilation and runtime environments of the microprocessor, reconfigurable processors and Linux operating system. This integrated software and hardware environment leads to higher application performance, reduced system footprint, lower power consumption, and dramatic total cost of ownership advantages.

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Intellectual Property

SRC's technology is protected by over 1,000 granted patent claims covering hardware, software and applications.

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Patents

Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
United States of America
6076152
System and method for dynamic priority conflict resolution in a multi-processor computer system having shared memory resources
United States of America
6026459
Split directory-based cache coherency technique for a multi-processor computer system
United States of America
6295598
Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
United States of America
6247110
Enhanced memory algorithmic processor architecture for multiprocessor computer systems
Australia
2001245761
Multiprocessor with each processor element accessing operands in loaded input buffer and forwarding results to fifo output buffer
United States of America
6339819
System and method for accelerating web site access and processing utilizing a computer system incorporating reconfigurable processors operating under a single operating system image
United States of America
6434687
System and method for accelerating web site access and processing utilizing a computer system incorporating reconfigurable processors operating under a single operating system image
Australia
2002303661
System and method for semaphore and atomic operation management in a multiprocessor
United States of America
6594736
Bandwidth enhancement for uncached devices
United States of America
6836823
System and method for dynamic priority conflict resolution in a multi-processor computer system
Canada
2317543
System and method for partitioning control-dataflor graph representations
United States of America
6964029
Efficiency of reconfigurable hardware
United States of America
6941539
Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
United States of America
6961841
Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
Canada
2313462
Interface for integrating reconfigurable processors into a general purpose computing system
United States of America
7155602
System and method for explicit communication of messages between processes running on different nodes in a clustered multiprocessor system
United States of America
7124211
Computer system architecture and memory controller for closecoupling within a hybrid processing system utilizing an adaptive processor interface port
United States of America
7003593
Process for converting programs in high-level programming languages to unified executable for hybrid computing platforms
United States of America
6983456
Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation
United States of America
7155708
System and method for providing an arbitrated memory bus in a hybrid computing system
United States of America
6996656
Map compiler pipelined loop structure
United States of America
7134120
System and method of enhancing efficiency and utilization of memory bandwidth in reconfigurable hardware
United States of America
7149867
System and method for accelerating web site access and processing utilizing a computer system incorporating reconfigurable processors operating under a single operating system image
Canada
2448223
System and method for converting control flow graph representations to controldataflow graph representations
United States of America
7299458
Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions
United States of America
7225324
Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors INA dual in-line memory module format
United States of America
7197575
Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
United States of America
7237091
Interface for integrating reconfigurable processors into a general purpose computing system
United States of America
7167976
Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors INA dual in-line memory module format
United States of America
7373440
Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors INA dual in-line memory module format
Japan
4128956
Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors INA dual in-line memory module format
United Kingdom
1442378
Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices
United States of America
7424552
Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors INA dual in-line memory module format
United States of America
7421524
Reconfigurable processor element utilizing both coarse and fine grained reconfigurable elements
United States of America
7406573
Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers
United States of America
7565461
Technique for improving the efficiency of recongifurable hardware
Japan
4330535
Map compiler pipelined loop structure
Japan
4330582
Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions
United States of America
7620800
Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation
Japan
4403080
System and method for explicit communication of messages between processes running on different nodes in a clustered multiprocessor system
Japan
4416658
Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions
Japan
4430544
Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM)
United States of America
7680968
Process for converting programs in high-level programming languages to unified executable for hybrid computing platforms
United States of America
7703085
Process for converting programs in high-level programming languages to unified executable for hybrid computing platforms
Japan
4482454
Dynamic priority conflict resolution in a multi-processor computer system having shared resources
United States of America
7890686
Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
Canada
2515283
Switch/network adapter port incorporating selectively accessible shared memory resources
France
1652058
Switch/network adapter port incorporating selectively accessible shared memory resources
Germany (Federal Republic of)
1652058
Switch/network adapter port incorporating selectively accessible shared memory resources
United Kingdom
1652058
The memory controller also deinterleaved reconstitutable processing elements to be used for one or more of the microprocessor 1 coupled to a switch/network adapter
Japan
4703189
System and method for accelerating web site access and processing utilizing a computer system incorporating reconfigurable processors operating under a single operating system image
Japan
4713080
Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
Japan
4921638
System and method for accelerating web site access and processing utilizing a computer system incorporating reconfigurable processors operating under a single operating system image
Japan
4990244
Process for converting programs in high-level programming languages to unified executable for hybrid computing platforms
Japan
5036801
Elimination of stream consumer loop overshoot effects
United States of America
8589666
Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
Japan
5364543
Computer system
Japan
5408677
System and method for computational unification of heterogeneous implicit and explicit processing elements
United States of America
8713518
System and method of enhancing efficiency and utilization of memory bandwidth in reconfigurable hardware
France
1639474
System and method of enhancing efficiency and utilization of memory bandwidth in reconfigurable hardware
Germany (Federal Republic of)
1639474
System and method of enhancing efficiency and utilization of memory bandwidth in reconfigurable hardware
United Kingdom
1639474
Reconstitutible processing technique, low power consumption, and a mobile electronic device capable of high speed applications
Japan
5630772
System and method for computational unification of heterogeneous implicit and explicit processing elements
United States of America
8930892
Multi-processor computer architecture incorporating distributed multi-ported common memory modules
Japan
5729740
System and method for retaining dram data when reprogramming reconfigurable devices with dram memory controllers
Japan
5777040
System and method for retaining dram data when reprogramming reconfigurable devices with dram memory controllers
United States of America
9153311
System and method for computational unification of heterogeneous implicit and explicit processing elements
Japan
5818351
System and method for thermally coupling memory devices to a memory controller INA computer memory board
Japan
5826956
Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
France
1038253
Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
Germany (Federal Republic of)
1038253
Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
United Kingdom
1038253
Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
European Patent
1038253
Multi-processor computer architecture incorporating distributed multi-ported common memory modules
Australia
2014202193
System and method for retaining dram data when reprogramming reconfigurable devices with dram memory controllers incorporating a data maintenance block colocated with a memory module or subsystem
United States of America
9530483
System and method for accelerating web site access and processing utilizing a computer system incorporating reconfigurable processors operating under a single operating system image
European Patent
Technique for improving the efficiency of recongifurable hardware
European Patent
System and method for computational unification of heterogeneous implicit and explicit processing elements
European Patent
Mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption
United States of America
Mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption
European Patent
Multi-processor computer architecture incorporating distributed multi-ported common memory modules
United States of America
Multi-processor computer architecture incorporating distributed multi-ported common memory modules
Australia
Multi-processor computer architecture incorporating distributed multi-ported common memory modules
Canada
Multi-processor computer architecture incorporating distributed multi-ported common memory modules
European Patent
System and method for thermally coupling memory devices to a memory controller ina computer memory board
United States of America
System and method for thermally coupling memory devices to a memory controller ina computer memory board
European Patent
System and method for retaining dram data when reprogramming reconfigurable devices with dram memory controllers
European Patent
FPGA based data and currency exchange
United States of America
FPGA based data and currency exchange
Canada
System and method for retaining dram data when reprogramming reconfigurable devices with dram memory controllers incorporating a data maintenance block colocated with a memory or module or subsystem
Patent Cooperation Treaty
FPGA platform as a service (PAAS)
United States of America